2026 RISC-V 中国峰会（RVSC2026）演说征集（CFP）

RISC-V Summit China 2026 (RVSC2026) Call for Presentations (CFP)

大会主办方：RISC-V国际开源实验室

The Organizer：RISC-V International Open-Source Laboratory

大会时间：2026 年 10 月 18 日-20 日

Conference Dates: October 18-20, 2026

大会地点：深圳会展中心（福田）

Venue: Shenzhen Convention & Exhibition Center (Futian)

2026 RISC-V 中国峰会学术与产业议题全面征集现已启动。我们诚邀全球学术界泰斗、产业领袖、开源社区开发者提交前沿演说申请！

The call for academic and industry topics for RISC-V Summit China 2026 has now officially launched. We warmly invite leading scholars, industry leaders, and open-source community developers from around the world to submit proposals for cutting-edge presentations.

投稿链接

Submission Link

https://sessionize.com/risc-v-summit-china-2026-copy/

核心时间节点

Key Dates

阶段　截止日期/通知时间　状态

Stage Deadline / Notification Date Status

投稿截止日期　2026 年 8 月 31 日（AoE）　开放投递中（Open）

Submission Deadline August 31, 2026 (AoE) Open for submissions

评审结果通知　2026 年 9 月 21 日　准备中

Review Results Notification September 21, 2026 In preparation

峰会举办日期　2026 年 10 月 18 日-20 日　准备中

Summit Dates October 18-20, 2026 In preparation

7 大分论坛征集方向

Call for Topics across Seven Forums

请根据您的研究或产业方向，选择对应的分论坛提交议题：

Please select the appropriate forum based on your research or industry area when submitting your topic:

各分论坛均欢迎学术研究成果与产业落地报告两类投稿。已在同行评审会议（如 ISCA、MICRO、HPCA、ASPLOS、DAC、PLDI/CGO 等）上发表的工作明确欢迎投稿；程序委员会将在议程编排中有意将研究成果与部署实践并置呈现。

Each track welcomes both academic research contributions and industrial deployment reports. Work previously presented at peer-reviewed venues (e.g., ISCA, MICRO, HPCA, ASPLOS, DAC, PLDI/CGO) is explicitly welcome; the program committee will deliberately program research results alongside deployment experience within sessions.

1. 1. 人工智能分会场（人工智能分会场（Track on Artificial IntelligenceTrack on Artificial Intelligence））

范围： 聚焦 RISC-V 在 AI 计算全栈中的角色——从矩阵 / 向量扩展的指令集标准化、编译器与算子库，到 AI 框架与运行时，再到云端集群与端侧异构部署的系统集成。议题应兼顾标准化进展与真实产品 / 部署案例。同样欢迎面向矩阵/向量加速的体系结构与编译器研究成果，包括已在同行评审会议上发表的工作。

Scope: Focuses on RISC-V's role across the full AI computing stack — from ISA standardization of matrix / vector extensions, compilers and operator libraries, to AI frameworks and runtimes, and on to system integration of cloud clusters and heterogeneous edge deployment. Sessions should balance standardization progress with real product / deployment cases. Architecture and compiler research on matrix / vector acceleration — including work published at peer-reviewed venues — is equally in scope.

2. 2. 数据中心 / 高性能计算分会场（数据中心 / 高性能计算分会场（Track on Datacenter / HPCTrack on Datacenter / HPC））

范围： 聚焦应用级RISC-V 在数据中心与高性能计算的平台化落地：服务器 SoC 与平台规范、固件与启动（UEFI / ACPI / SBI）、内存与互连（含 CXL）、虚拟化与云原生编排、机密计算与可信执行、HPC 并行框架与可扩展性。同样欢迎面向可扩展 RISC-V 系统的服务器级微架构、内存与互连体系结构及系统软件方面的研究成果。

Scope: Focuses on platform-level deployment of application-class RISC-V in datacenter and high-performance computing: server SoC and platform specifications; firmware and boot (UEFI / ACPI / SBI); memory and interconnect (including CXL); virtualization and cloud-native orchestration; confidential computing and trusted execution; HPC parallel frameworks and scalability. Research contributions on server-class microarchitecture, memory and interconnect architecture, and system software for scalable RISC-V systems are equally in scope.

3. 3. 软件生态分会场（Track on Software Ecosystem）软件生态分会场（Track on Software Ecosystem）

范围： 覆盖从工具链、内核、固件到发行版与上层运行时的通用软件生态，以及托管 / 语言运行时（JVM、V8、.NET、Python、Rust、Go）、JIT、调试与性能分析工具链、多发行版与软件包生态。凸显可移植的软件使能与生态成熟度。同样欢迎编译技术、运行时系统与性能分析方面的研究成果，包括已发表的学术工作。

Scope: Covers the general-purpose software ecosystem from toolchains, kernel, and firmware to distributions and upper-layer runtimes — the horizontal layer underpinning every vertical application, as well as managed / language runtimes (JVM, V8, .NET, Python, Rust, Go); JITs; debugging and performance-analysis toolchains; multi-distribution and software-package ecosystems. Focuses on portable software enablement and ecosystem maturity. Research on compilation techniques, runtime systems, and performance analysis — including previously published academic work — is equally in scope.

4. 4. 芯片设计与验证分会场（Track on Design and Verification）芯片设计与验证分会场（Track on Design and Verification）

范围： 覆盖从微架构与 RTL 设计、敏捷开发方法学（Chisel/SpinalHDL），到硅前 / 形式化验证、一致性（compliance）与合规测试、原型（FPGA / 仿真）与流片的完整设计—验证链路。同时涵盖 EDA 工具，尤其突出开源 EDA 与开源 RISC-V 核生态，以及面向规范一致性的验证方法学。

Scope: Covers the full design-verification chain — from microarchitecture and RTL design and agile methodologies (Chisel / SpinalHDL), to pre-silicon / formal verification, conformance (compliance) testing, prototyping (FPGA / simulation), and tape-out. Also covers EDA tooling, with particular emphasis on open-source EDA and the open-source RISC-V core ecosystem, along with conformance-oriented verification methodology.

5. 5. 汽车电子、工业与机器人分会场（Track on Automotive, Industrial & Robotics）汽车电子、工业与机器人分会场（Track on Automotive, Industrial & Robotics）

范围： 面向安全关键与实时嵌入式领域的 RISC-V 落地，涵盖车载电子电气架构、工业控制、机器人运动与感知、低空经济与航空航天。功能安全（ISO 26262 / IEC 61508）、实时性与确定性、安全关键认证、车规级软件栈与 AUTOSAR 适配。

Scope: Targets RISC-V deployment in safety-critical and real-time embedded domains, covering automotive E/E architectures, industrial control, robotic motion and perception, the low-altitude economy, and aerospace. Functional safety (ISO 26262 / IEC 61508), real-time determinism, and safety-critical certification, as well as automotive-grade software stacks and AUTOSAR adaptation.

6. 6. 嵌入式、物联网与智能硬件分会场（Track on Embedded, IoT & Smart Hardware）嵌入式、物联网与智能硬件分会场（Track on Embedded, IoT & Smart Hardware）

范围： 面向资源受限与成本敏感的嵌入式与 IoT 量产场景，涵盖 MCU 级 RISC-V、RTOS 与裸机软件、低功耗与电源管理、无线连接、端侧 AI（TinyML）、设备安全与可信启动、量产与供应链，以及各种消费类电子产品的最新产业化进展等。

Scope: Targets resource-constrained, cost-sensitive embedded and IoT volume-production scenarios, covering MCU-class RISC-V; RTOS and bare-metal software; low power and power management; wireless connectivity; on-device AI (TinyML); device security and trusted boot; and mass production and supply chain, as well as the latest industrialization progress of various consumer electronic products.

7. 7. 产学合作与创新创业分会场（Track on Industry-Academia Collaboration, Innovation & Entrepreneurship）产学合作与创新创业分会场（Track on Industry-Academia Collaboration, Innovation & Entrepreneurship）

范围： 覆盖 RISC-V 人才培养与课程建设、高校与科研机构的前沿研究、开源社区与标准组织协作、初创企业与投融资生态等

Scope: Covers RISC-V talent development and curriculum building; frontier research at universities and research institutes; open-source community and standards-body collaboration; and the startup and investment ecosystem.